View TLE6389-G50_2358750.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

step-down dc/dc controller preliminary data sheet tle 6389 preliminary data sheet rev. 1.0 1 2003-05-05 type ordering code package description tle 6389 gv q67006-a9542 p-dso-14-3 adjustable tle 6389 g50 q67006-a9545 p-dso-14-3 5v, ro-hysteresis << tle 6389 g50-1 q67006-a9635 p-dso-14-3 5v, ro-hysteresis 1v m1 d1 c out = 100 f v out c bds = 220 nf v in l 1 = 47 h gdrv bds fb gnd si_enable vs c in1 = 100 f on off cs r sense = 0.05 m1: infineon bso613spv infineon bsp613p d1: motorola mbrd360 l1: epcos b82479-a1473-m coilcraft do3340p-473 c in1 : electrolythic c in2 : ceramic c out : low esr tantalum si_gnd si r si1 = 400k c in2 = 220nf r si2 = 100k ro so rd c rd =100nf sync v out i out tle6389g50-1 11 14 12 2 3 9 10 8 4 5 1 7 13 6 vout 1overview 1.1 features ? input voltage range from < 5v up to 60v ? output voltage versions: 5v fixed and adjustable ? output voltage accuracy: 3% ? load current peak determined by sense resistor ? output power up to 15w and above ? 100% maximum duty cycle ? less than 100a quiescent current at low loads ? 2a max. shutdown current at device off ? fixed 350khz switching frequency ? frequency synchronization input for external clocks ? current mode control scheme ? integrated output under voltage reset circuit with adjustable delay time ? on chip low battery detector (on chip comparator) ? automotive temperature range
tle 6389 preliminary data sheet rev. 1.0 2 2003-05-05 1.2 short functional description the tle6389 step-down dc-dc switching controllers provide high efficiency over loads ranging from 1ma up to 3a. a unique pwm/pfm control scheme operates with up to a 100% duty cycle, resulting in very low dropout voltage. this control scheme eliminates minimum load requirements and reduces the supply current under light loads to 100a. for the start up procedure a slow start feature is implemented to avoid overshoots at the output. the tle6389 step-down controllers drive an external p-channel mosfet, allowing design flexibility for applications up to 15w of output power. a high switching frequency and operation in continuous-conduction mode allow the use of tiny surface- mount inductors. output capacitor requirements are also reduced, minimizing pc board area and system costs. the output voltage is preset at 5v ( tle6389g50-1 and tle6389g50 ) and adjustable for the tle6389gv . input voltages can be up to 60v. 1.3 pin configuration (top view ) 8 9 10 11 12 7 6 5 4 3 2 13 1 14 p-d-so-14 enable / si_enable fb vout gnd sync si_gnd si cs vs gdrv bds ro so rd
tle 6389 preliminary data sheet rev. 1.0 3 2003-05-05 1.4 basic block diagram internal power supply and biasing battery sense and undervoltage reset voltage reference block pwm / pfm regulator clock generator so ro fb vout g drv cs sync si ena ble si- gnd bds gnd rd vs tle 6389gv driver
tle 6389 preliminary data sheet rev. 1.0 4 2003-05-05 1.5 pin definitions and functions pin no so-14 symbol function 1 enable active-high enable input (only at adjustable version, tle6389gv) for the device. the device is shut down when enable is driven low. in this shut down- mode the reference, the output and the external mosfet are turned off. connect to logic high for normal operation. 1si_ena ble active-high enable input (only at 5v version, tle6389g50-1 and tle6389g50) for si_gnd input. si_gnd is switched to high impedance when si_enable is low. high level at si_enable connects si_gnd to gnd with low impedance. so is undefined when si_enable is low. 2fb feedback input. 1. for adjustable version (gv) connect this pin to an external voltage divider from the output to gnd (see the determining the output voltage, application section). 2. at the 5v fixed output voltage version (g50-1 and g50) the fb is connected internally to an on-chip voltage divider. it does not have to be connected externally to the output. 3vout buck output voltage input. input for the internal supply. connect to the output capacitance of the buck converter. 4gnd ground connection. analog signal ground. 5sync input for external frequency synchronization. an external clock signal connected to this pin allows switching frequency synchronization of the device. the internal oscillator is clocked then by the frequency applied at the sync input. 6si_gnd si-ground input. ground connection for si comparator resistor divider. depending on si_enable this input is switched to high impedance or low ohmic to gnd. 7si sense comparator input. input of the low-battery comparator. this input is compared to an internal 1.25v reference where so gives the result of the comparison. can be used for any comparison, not necessarily as battery sense. 8rd reset delay input. connect a ceramic capacitor to gnd for power on reset delay time adjustment.
tle 6389 preliminary data sheet rev. 1.0 5 2003-05-05 9so sense comparator output. open drain output from si comparator at the adjustable version (tle6389gv), pull down structure with an internal 20k ? pull up resistor to vout at the 5v version (tle6389g50-1 and tle6389g50). 10 ro reset output. open drain output from undervoltage reset comparator at the adjustable version (tle6389gv), pull down structure with an internal 20k ? pull up resistor to vout at the 5v version (tle6389g50-1 and tle6389g50). 11 bds buck driver supply input. connect a ceramic capacitor between bds and vs to generate clamped gate-source voltage to supply the driver of the pmos power stage. 12 gdrv gate drive output. connect to the gate of the external p-channel mosfet . the voltage at gdrv swings between the levels of vs and bds. 13 vs device supply input. connect a 220nf ceramic cap close to the pin in addition to the low esr tantalum input capacitance. 14 cs current-sense input. connect current-sense resistor between vs and cs. the voltage drop over the sense-resistor determines the peak current flowing in the buck circuit. the external mosfet is turned off when the peak current is exceeded. pin no so-14 symbol function
tle 6389 preliminary data sheet rev. 1.0 6 2003-05-05 2 absolute maximum ratings item parameter symbol limit values unit remarks min. max. device supply input vs 2.1 voltage v vs -0.3 61 v ? 2.2 current i vs ?? ? current sense input cs 2.3 voltage v cs -0.3 61 v ? 2.4 current i cs ?? ? gate drive output gdrv 2.5 voltage v gdrv ? 0.3 6.8 v |v vs ? v gdrv |<6.8v 2.6 current i gdrv ?? ? limited internally buck driver supply input bds 2.7 voltage v bds ? 0.3 55 v |v vs ? v bds |<6.8v 2.8 current i bds ?? ? feedback input fb 2.9 voltage v fb ? 0.3 6.8 v 2.10 current i fb ?? ? enable input si_enable 2.11 voltage v si_enab le ? 0.3 61 v (tle6389g50-1 and tle6389g50) 2.12 current i si_enabl e ??? si-ground input si_gnd 2.13 voltage v si_gnd ? 0.3 61 v (tle6389g50-1 and tle6389g50) 2.14 current i si_gnd ??? enable input enable 2.15 voltage v enable ? 0.3 61 v ( tle6389gv only) 2.16 current i enable ?? ?
tle 6389 preliminary data sheet rev. 1.0 7 2003-05-05 sense comparator input si 2.17 voltage v si ? 0.3 61 v 2.18 current i si ?? ? sense comparator output so 2.19 voltage v so ? 0.3 6.8 v 2.20 current i so ?? ? limited internally buck output voltage input vout 2.21 voltage v vout ? 0.3 15 v ( tle6389gv only) 2.22 voltage v vout ? 0.3 6.8 v (tle6389g50-1 and tle6389g50) 2.23 current i vout ?? ma reset delay input rd 2.24 voltage v rd ? 0.3 6.8 v 2.25 current i rd ?? ma reset output ro 2.26 voltage v ro ? 0.3 6.8 v 2.27 current i ro ?? ma limited internally frequency synchronization input sync 2.28 voltage v sync ? 0.3 6.8 v 2.29 current i sync ?? ma esd-protection (human body model; r=1,5k ? ; c=100pf) 2.30 electrostatic discharge voltage v esd ?2 2 kv hbm 2 absolute maximum ratings (cont?d) item parameter symbol limit values unit remarks min. max.
tle 6389 preliminary data sheet rev. 1.0 8 2003-05-05 note: maximum ratings are absolute ratings; exceeding any one of these values may cause irreversible damage to the integrated circuit. temperatures 2.31 junction temperature t j ? 40 150 c? 2.32 storage temperature t stg ? 50 150 c? 2 absolute maximum ratings (cont?d) item parameter symbol limit values unit remarks min. max.
tle 6389 preliminary data sheet rev. 1.0 9 2003-05-05 3 operating range item parameter symbol limit values unit remarks min. max. 3.1 supply voltage range v vs 560v 3.2 sense resistor r sense 5- m ? calculation see section 6 3.3 pmos, on+off delay t on+off delay -t min - 300 ns t min =v vout / (v vs *f sw ) 3.4 buck driver supply capacitor c bds 220 - nf 3.5 buck inductance l1 47 - h recommended value 3.6 buck inductance l1 22 100 h 3.7 buck output capacitor c out 100 - f 3.8 junction temperature t j ? 40 150 c thermal resistance 3.9 junction ambient r thj-a 140 k/w footprint only 3.10 junction pin r thj-p 50 k/w ?
tle 6389 preliminary data sheet rev. 1.0 10 2003-05-05 4 electrical characteristics 5v< v s <48v; - 40c< t j <150c; all voltages with respect to ground; positive current defined flowing into the pin; unless otherwise specified item parameter symbol limit values unit test condition min. typ. max. current consumption 1) tle6389g50-1 and tle6389g50 4.1 current consumption of vs i vs 75 90 a v vs = 48v; pfm mode; t j = 25 c 4.2 70 85 a v vs = 13.5v; pfm mode; t j = 25 c 4.3 115 a v vs = 48v; pfm mode 4.4 current consumption of si_enable i si_enable 510a v vs = 48v; v si_enable = 48v; pfm mode; t j = 25 c 4.5 current consumption of vout i vout 95 115 a v si_enable = l; v vout = 5.5v; pfm mode; t j = 25 c 4.6 140 160 a v si_enable = h; v vout = 5.5v; v si > v si, high ; pfm mode; t j = 25 c 4.7 current consumption of si i si 0.2 0.5 a v vs = 13.5v; v si_enable = h; v si = 10v ; pfm mode;
tle 6389 preliminary data sheet rev. 1.0 11 2003-05-05 current consumption 1) tle6389gv (variable) 4.8 current consumption of vs i vs 75 90 a v vs = 48v; v enable = h; pfm mode; t j = 25 c; v out > 7v 4.9 70 85 a v vs = 13.5v; v enable = h; pfm mode; t j = 25 c; v out > 7v 4.10 125 a v vs = 48v; v enable = h; pfm mode; v out > 7v 4.11 2 a v enable =0v 4.12 current consumption of enable i en 510a v vs = 48v; v enable = h; pfm mode; t j = 25 c 4.13 current consumption of vout i vout 140 160 a v out = 10v; v enable = h; v si > v si, high ; pfm mode; t j = 25 c; v out > 7v 4.14 current consumption of si i si 0.2 0.5 a v vs = 13.5v; v enable = h; v si = 10v ; pfm mode; t j = 25 c 4 electrical characteristics (cont?d) 5v< v s <48v; - 40c< t j <150c; all voltages with respect to ground; positive current defined flowing into the pin; unless otherwise specified item parameter symbol limit values unit test condition min. typ. max.
tle 6389 preliminary data sheet rev. 1.0 12 2003-05-05 4.15 current consumption of fb i fb 0.2 0.5 a v vs = 13.5v; v fb = 1.25v; v enable = h; pfm mode; t j = 25 c buck controller 4.16 output voltage v vout 4.85 5.00 5.15 v tle6389g50-1, tle6389g50; v vs = 13.5v & 48v; i out = 0.5 to 2a; pwm mode; r sense = 0.01 ? ; r m1 = 0.25 ? ; r l1 = 0.1 ? ; 4.17 4.75 5.00 5.25 v tle6389g50-1, tle6389g50; v vs = 24v; i out = 15ma; pfm mode; r sense = 0.01 ? ; r m1 = 0.25 ? ; r l1 = 0.1 ? ; 4.18 3.8 v tle6389g50-1; v vs decreasing from 5.8v to 4.2v; i load = 0ma to 500ma; r sense = 0.01 ? ; r m1 = 0.4 ? ; r l1 = 0.1 ? ; 4 electrical characteristics (cont?d) 5v< v s <48v; - 40c< t j <150c; all voltages with respect to ground; positive current defined flowing into the pin; unless otherwise specified item parameter symbol limit values unit test condition min. typ. max.
tle 6389 preliminary data sheet rev. 1.0 13 2003-05-05 4.19 fb threshold voltage v fb, th 1.225 1.25 1.275 v tle6389gv 4.20 output voltage v vout 9.7 10.0 10.3 v tle6389gv; calibrated divider, see section 7.3 ; v vs = 13.5v & 48v; i out = 0.5 to 2a; pwm mode; r sense = 0.01 ? ; r m1 = 0.25 ? ; r l1 = 0.1 ? ; 4.21 output voltage v vout 9.5 10.0 10.5 v tle6389gv; calibrated divider, see section 7.3 ; v vs = 24v; i out = 15ma; pfm mode; r sense = 0.01 ? ; r m1 = 0.25 ? ; r l1 = 0.1 ? ; 4.22 buck output voltage adjust range v vout v fb, th 7 v tle6389gv, supplied by vs only, complete current to supply the ic drawn from vs, 2) 4 electrical characteristics (cont?d) 5v< v s <48v; - 40c< t j <150c; all voltages with respect to ground; positive current defined flowing into the pin; unless otherwise specified item parameter symbol limit values unit test condition min. typ. max.
tle 6389 preliminary data sheet rev. 1.0 14 2003-05-05 4.23 buck output voltage adjust range v vout 7 15 v tle6389gv, current to supply the ic drawn from vs and vout, as specified, 2) 4.24 buck output voltage accuracy v vout 0.97 *v out _nom 1.03 *v out _nom v tle6389gv, pwm mode, 2) 4.25 buck output voltage accuracy v vout 0.95 *v out _nom 1.05 *v out _nom v tle6389gv, pfm mode, 2) 4.26 line regulation ? v vout / ? v vs 0.7 2 mv/ v v vs = 5.8 v to 48v; i out = 0.5 to 2a; pwm mode 4.27 load regulation ? v vout / ? i load 40 mv/ a tle6389g50-1 , tle6389g50 , i out = 0.5 to 2a; pwm mode; v vs = 5.8 v and 48v; r sense =0.01 ? 4.28 8* v out _nom mv/ a tle6389gv, i out = 0.5 to 2a; pwm mode; v vs = 13.5 v and 48v; r sense =0.01 ? 4.29 gate driver, pmos off v vs ? v gdrv 00.2v v enable/ si_enable = 5 v c bds = 220 nf c gdrv = 4.7nf 4 electrical characteristics (cont?d) 5v< v s <48v; - 40c< t j <150c; all voltages with respect to ground; positive current defined flowing into the pin; unless otherwise specified item parameter symbol limit values unit test condition min. typ. max.
tle 6389 preliminary data sheet rev. 1.0 15 2003-05-05 4.30 gate driver, pmos on v vs ? v gdrv 68.2v v enable/ si_enable = 5 v c bds = 220 nf c gdrv = 4.7nf 4.31 gate driver, uv lockout v vs ? v bds 2.5 4 v decreasing (v vs -v bds ) until gdrv is permanently at vs level 4.32 gate driver, peak charging current i gdrv 1apmos dependend; 2) 4.33 gate driver, peak discharging current i gdrv 1apmos dependend; 2) 4.34 gate driver, gate voltage, rise time t r 45 60 ns v enable/ si_enable = 5 v c bds = 220 nf c gdrv = 4.7nf 4.35 gate driver, gate voltage, fall time t f 50 65 ns v enable/ si_enable = 5 v c bds = 220 nf c gdrv = 4.7nf 4.36 peak current limit threshold voltage v lim = v vs ? v cs 50 80 100 mv 4.37 oscillator frequency f osc 290 360 420 khz pwm mode only 4.38 maximum duty cycle d max 100 % pwm mode only 4.39 minimum on time t min 220 400 ns pwm mode only 4.40 sync capture range 250 530 khz pwm mode only 4 electrical characteristics (cont?d) 5v< v s <48v; - 40c< t j <150c; all voltages with respect to ground; positive current defined flowing into the pin; unless otherwise specified item parameter symbol limit values unit test condition min. typ. max.
tle 6389 preliminary data sheet rev. 1.0 16 2003-05-05 reset generator 4.41 reset threshold v vout, rt 3.5 3.65 3.8 v tle6389g50-1; v vout decreasing 4.42 4.5 4.65 4.8 v tle6389g50-1; v vout increasing 4.43 reset threshold v vout, rt 4.5 4.65 4.8 v tle6389g50; v vout increasing/ decreasing 4.44 reset threshold hysteresis ? v vout, rt 50 mv tle6389g50; 4.45 reset threshold v fb, rt 1.12 v tle6389gv; v vout decreasing 4.46 1.17 v tle6389gv; v vout increasing 4.47 reset output pull up resistor r ro 10 20 40 k ? tle6389g50-1, tle6389g50; internally connected to v out 4.48 reset output high voltage v ro, h 0.8* v vout v tle6389g50-1, tle6389g50; i roh =0ma 4.49 reset output low voltage v ro,l 0.2 0.4 v i ro, l =1ma; 2.5v < v vout < v rt 4 electrical characteristics (cont?d) 5v< v s <48v; - 40c< t j <150c; all voltages with respect to ground; positive current defined flowing into the pin; unless otherwise specified item parameter symbol limit values unit test condition min. typ. max.
tle 6389 preliminary data sheet rev. 1.0 17 2003-05-05 4.50 reset output low voltage v ro,l 0.2 0.4 v i ro, l =0.2ma; 1v < v vout < 2.5v 4.51 reset delay charging current i rd, ch 510a v rd = 0v 4.52 reset delay discharging current i rd, dis 313ma 4.53 upper reset timing threshold v rd, ut 2.6 4.8 v 4.54 lower reset timing threshold v rd, lt 00.2v 4.55 reset delay time t rd 26 96 ms calculated with c rd = 100nf; 2) ; see section 6 4.56 reset reaction time t rr 10 s overvoltage lockout 4.57 overvoltage threshold v vout, ov v out _nom +0.1 v tle6389g50-1, tle6389g50; v vout increasing 4.58 overvoltage threshold v fb, ov v fb, th_nom +0.02 v tle6389gv; v vout increasing enable input 4.59 enable on- threshold v enable, on 4.5 v 4.60 enable off- threshold v enable, off 0.8 v 4 electrical characteristics (cont?d) 5v< v s <48v; - 40c< t j <150c; all voltages with respect to ground; positive current defined flowing into the pin; unless otherwise specified item parameter symbol limit values unit test condition min. typ. max.
tle 6389 preliminary data sheet rev. 1.0 18 2003-05-05 si_enable input 4.61 enable on- threshold v enable, on 4.5 v 4.62 enable off- threshold v enable, off 0.8 v si_gnd input 4.63 switch on resistance r sw 50 100 230 ? v si_enable =5v; i si_gnd = 3ma; battery voltage sense 4.64 sense threshold v si, low 1.22 1.25 1.28 vv vs decreasing 4.65 sense threshold v si, high 1.33 vv vs increasing 4.66 sense threshold hysteresis v si, hys 50 80 120 mv 4.67 sense output pull up resistor r so 10 20 40 k ? tle6389g50-1, tle6389g50; internally connected to v vout 4.68 sense out output high voltage v so, h 0.8* v vout v i so, h =0ma 4.69 sense out output low voltage v so, l 0.2 0.4 v i so, l =1ma; 2.5v < v vout ; v si <1.13v 4.70 0.4 v vout vi sol =0.2ma; 1v < v vout <2.5v; v si <1.13v 4 electrical characteristics (cont?d) 5v< v s <48v; - 40c< t j <150c; all voltages with respect to ground; positive current defined flowing into the pin; unless otherwise specified item parameter symbol limit values unit test condition min. typ. max.
tle 6389 preliminary data sheet rev. 1.0 19 2003-05-05 thermal shutdown 4.71 thermal shutdown junction temperature t jsd 151 175 200 c 4.72 temperature hysteresis ? t30k 1) the device current measurements for i vs and i fb exclude mosfet driver currents. 2) not subject to production test - specified by design 4 electrical characteristics (cont?d) 5v< v s <48v; - 40c< t j <150c; all voltages with respect to ground; positive current defined flowing into the pin; unless otherwise specified item parameter symbol limit values unit test condition min. typ. max.
tle 6389 preliminary data sheet rev. 1.0 20 2003-05-05 5 typical performance characteristics current consumption i vs vs. temperature t j at enabled device and v vs =13.5v current consumption i vs vs. temperature t j at enabled device and v vs =48v current consumption i vout vs. temperature t j at enabled device and v vout =5.5v current consumption i vout vs. temperature t j at enabled device and v vout =10v (gv) -50 -20 10 40 70 100 130 160 t j c i vs a 20 30 40 50 60 70 80 90 -50 -20 10 40 70 100 130 160 t j c i vs a 40 50 60 70 80 90 100 110 -50 -20 10 40 70 100 130 160 t j c i vout a 110 120 130 140 150 160 170 180 -50 -20 10 40 70 100 130 160 t j c i vout a 90 100 110 120 130 140 150 160
tle 6389 preliminary data sheet rev. 1.0 21 2003-05-05 internal oscillator frequency f osc vs. temperature t j minimum on time t min (blanking) vs. temperature t j peak current limit threshold voltage v lim vs. temperature t j ) gate driver supply v vs - v bds vs. temperature t j -50 -20 10 40 70 100 130 160 t j c f osc khz 310 320 380 330 340 350 360 370 -50 -20 10 40 70 100 130 160 t j c t min ns 175 200 350 225 250 275 300 325 -50 -20 10 40 70 100 130 160 t j c v lim mv 40 50 60 70 80 90 100 110 -50 -20 10 40 70 100 130 160 t j c v vs -v bds v 7.2 7.4 7.6 7.8 8.0 8.2 8.4 8.6
tle 6389 preliminary data sheet rev. 1.0 22 2003-05-05 output voltage v vout vs. temperature t j in pfm mode (v vs =24v, i load =15ma, g50-1) lower reset threshold v vout, rt vs. temperature t j (g50-1) lower reset threshold v fb,rt vs. temperature t j (gv) internal pull up resistors r ro and r so vs. temperature t j (g50-1) -50 -20 10 40 70 100 130 160 t j c v vout v 4.80 4.85 5.15 4.90 4.95 5.00 5.05 5.10 -50 -20 10 40 70 100 130 160 t j c v vout,rt v 3.58 3.60 3.72 3.62 3.64 3.66 3.68 3.70 -50 -20 10 40 70 100 130 160 t j c v fb,rt v 1.07 1.08 1.14 1.09 1.10 1.11 1.12 1.13 -50 -20 10 40 70 100 130 160 t j c r ro k ? 10 15 20 25 30 35 40 45 r so k ?
tle 6389 preliminary data sheet rev. 1.0 23 2003-05-05 lower sense threshold v si, low vs. temperature t j on resistance of si_gnd switch r sw vs. temperature t j -50 -20 10 40 70 100 130 160 t j c v si,low v 1.21 1.22 1.23 1.24 1.25 1.26 1.27 1.28 -50 -20 10 40 70 100 130 160 t j c r sw ? 0 40 280 80 120 160 200 240
tle 6389 preliminary data sheet rev. 1.0 24 2003-05-05 6 detailed circuit description in the following, some internal blocks of the tle6389 are described in more detail. for the right choice of the external components please refer to the section application infomation. 6.1 pfm/pwm step-down regulator to meet the strict requirements in terms of current consumption demanded by all body- and 42v powernet applications a special pfm (pulse frequency modulation) - pwm (pulse width modulation) control scheme for highest efficiency is implemented in the tle6389 regulators. under light load conditions the output voltage is able to increase slightly and at a certain threshold the controller jumps into pfm mode. in this pfm operation the pmos is triggered with a certain on time (depending on input voltage, output voltage, inductance- and sense resistor value) whenever the buck output voltage decreases to the so called wake-threshold. the switching frequency of the step down regulator is determined in the pfm mode by the load current. it increases with increasing load current and turns finally to the fixed pwm frequency at a certain load current depending on the input voltage, current sense resistor and inductance. the diagram below shows the buck regulation circuit of the tle6389 . figure 1 buck control scheme the tle6389 uses a slope-compensated peak current mode pwm control scheme in which the feedback or output voltage of the step down cirucit and the peak current of the current through the pmos are compared to form the off signal for the external pmos. vref vfb vs bds gdrv current- sense amplifier + mux cs vs error amplifier pwm comparator slope- compensation blanking r s q +- + - >1 & +- +- over- voltage lockout over- temp. shutdown vref vfb, ov vref vdiode - + wake- comparator vref vfb, wk oscillator sync mode level- shift pfm pwm
tle 6389 preliminary data sheet rev. 1.0 25 2003-05-05 the on-trigger is set periodically by the internal oscillator when acting in pwm mode and is given by the output of the wake-comparator when operating in pfm mode. the multiplexer (mux) is switched by the output of the mode-detector which distinguishes between pfm and pwm by tracking the output voltage (goto pfm) and by tracking the gate trigger frequency (goto pwm). in pfm mode the peak current limit is reduced to prevent overshoots at the output of the buck regulator. in order to avoid a gate turn off signal due to the current peak caused by the parasitric capacitance of the catch diode the blanking filter is necessary. the blanking time is set internally to 200ns and determines (together with the pmos turn on and turn off delay) the minimum duty cycle of the device. in addition to the pfm/pwm regulation scheme an overvoltage lockout and thermal protection are implemented to guarantee safe operation of the device and of the supplied application circuit. 6.2 battery voltage sense to detect undervoltage conditions at the battery a sense comparator block is available within the tle6389. the voltage at the si input is compared to an internal reference of typ. 1.25v. the output of the comparator drives a nmos structure giving a low signal at so as soon as the voltage at si decreases below this threshold. in the 5v fixed version an internal pull up resistor is connected from the drain of the nmos to the output of the buck converter, in the variable version so is open drain. the sense in voltage divider can be switched to high impedance by a low signal at the si_enable to avoid high current consumption to gnd (tle6389g50-1 and tle6389g50 only). of course the sense comparator can be used for any input voltage and does not have to be used for the battery voltage sense only. 6.3 undervoltage reset the output voltage is monitored continously by the internal undervoltage reset comparator. as soon as the output voltage decreases below the thresholds given in the characteristics the npn structure pulls ro low (latched). in the 5v fixed version an internal pull up resistor is connected from the collector of the npn to the output of the buck converter, in the variable version ro is open collector. at power up ro is kept low until the the output voltage has reached its reset threshold and stayed above this threshold for the power on reset delay time. this delay time can be determined by the appropriate choice of the external delay capacitance (see application information).
tle 6389 preliminary data sheet rev. 1.0 26 2003-05-05 7 application information 7.1 general the tle6389 step-down dc-dc controllers are designed primarily for use in automotive applications where high input voltage range requirements have to be met. using an external p-mosfet and current-sense resistor allows design flexibility and the improved efficiencies associated with high-performance p-channel mosfets. the unique, peak current-limited, pwm/pfm control scheme gives these devices excellent efficiency over wide load ranges, while drawing around 100a current from the battery under no load condition. this wide dynamic range optimizes the tle6389 for automotive applications, where load currents can vary considerably as individual circuit blocks are turned on and off to conserve energy. operation to a 100% duty cycle allows the lowest possible dropout voltage, maintaining operation during cold cranking. high switching frequencies and a simple circuit topology minimize pc board area and component costs. 7.2 typical application circuits figure 2 application circuit tle6389g50-1 and tle6389g50 m1 d1 c out = 100 f v out c bds = 220 nf v in l 1 = 47 h gdrv bds fb gnd si_enable vs c in1 = 100 f on off cs r sense = 0.05 m1: infineon bso613spv infineon bsp613p d1: motorola mbrd360 l1: epcos b82479-a1473-m coilcraft do3340p-473 c in1 : electrolythic c in2 : ceramic c out : low esr tantalum si_gnd si r si1 = 400k c in2 = 220nf r si2 = 100k ro so rd c rd =100nf sync v out i out tle6389g50-1 11 14 12 2 3 9 10 8 4 5 1 7 13 6 vout
tle 6389 preliminary data sheet rev. 1.0 27 2003-05-05 figure 3 application circuit tle6389gv 7.3 output voltage at adjustable version - feedback divider the output voltage is sensed either by an internal voltage divider connected to the vout pin ( tle6389g50-1 and tle6389g50, fixed 5v versions) or an external divider from the buck output voltage to the fb pin ( tle6389gv , adjustable version). to determine the resistors of the feedback divider for the desired output voltage v out at the tle6389gv select r fb2 between 5k ? and 500k ? and obtain r fb1 with the following formula: v fb is the threshold of the error amplifier with its value of typical 1.25v which shows that the output voltage can be adjusted in a range from 1.25 to 15v. keep in mind that the current consumption will be increased in pfm mode in the range between 1.25 and 7v. to filter spikes at the fb input connect a small ceramic cap (10nf) in parallel to r fb2 . m1 d1 c out = 100 f v out c bds = 220 nf v in l 1 = 47 h tle6389gv gdrv bds vout gnd enable c in1 = 100 f on off cs r sense = 0.05 m1: infineon bso613spv infineon bsp613p d1: motorola mbrd360 l1: epcos b82479-a1473-m coilcraft do3340p-473 c in1 : electrolythic c in2 : ceramic c out : low esr tantalum r si1 = 400k c in2 = 220nf r si2 = 100k ro so rd c rd =100nf sync fb r fb1 = 330k r fb2 = 47k 11 13 7 si vs 14 12 3 9 10 2 8 4 5 1 si_gnd 6 to e.g. 5v rail r so = r ro = 20k to c r fb1 r fb2 v out v fb th , ---------------- 1 ? ? =
tle 6389 preliminary data sheet rev. 1.0 28 2003-05-05 7.4 si_enable connecting si_enable to 5v causes si_gnd to have low impedance. thus the si comparator is in operation and can be used to monitor the battery voltage. so output signal is valid. connecting si_enable to gnd causes si_gnd to have high impedance. thus the si comparator is not able to monitor the battery voltage. so output signal is invalid. 7.5 battery sense comparator - voltage divider the formula to calculate the resistor divider for the sense comparator is basically the same as for the feedback divider in section before. with the selected resistor r si2 , the desired threshold of the input voltage v in, uv and the lower sense threshold v si, low the resistor r si1 is given to: for high accuracy and low ohmic resistor divider values the on-resistance of the si_gnd nmos (typ. 100 ? ) has to be added to r si2 . 7.6 undervoltage reset - delay time the diagram below shows the typical behavour of the reset output in dependency on the input voltage v in , the output voltagev vout or v fb and the reset delay voltage v rd . r si1 r si2 v in uv , v si low , ------------------ - 1 ? ? =
tle 6389 preliminary data sheet rev. 1.0 29 2003-05-05 figure 4 reset timing the reset delay time can be calculated with the following: where c rd is the value of the delay capacitance, v rd,ut the upper reset timing threshold and i rd, ch the reset delay charging current. 7.7 100% duty-cycle operation and dropout the tle6389 operates with a duty cycle up to 100%. this feature allows to operate with the lowest possible drop voltage at low battery voltage as it occurs at cold cranking. the mosfet is turned on continuously when the supply voltage approaches the output voltage level, conventional switching regulators with less than 100% duty cycle would fail in that case. the drop- or dropout voltage is defined as the difference between the input and output voltage levels when the input is low enough to drop the output out of regulation. dropout t t t v vout, rt v fb,rt t rr < t rr t t rd thermal shutdown under voltage over load t rd t rd t rd v rd, ut v rd, lt v in v vout v fb v rd v ro t rd v rd ut , i rd ch , ------------------- - c rd ? =
tle 6389 preliminary data sheet rev. 1.0 30 2003-05-05 depends on the mosfet drain-to-source on-resistance, the current-sense resistor and the inductor series resistance. it is proportional to the load current: 7.8 sync input and frequency control the tle6389 ?s internal oscillator is set for a fixed pwm switching frequency of 360khz or can be synchronized to an external clock at the sync pin. when the internal clock is used sync has to be connected to gnd. sync is a negative-edge triggered input that allows synchronization to an external frequency ranging between 270khz and 530khz. when sync is clocked by an external signal, the converter operates in pwm mode until the load current drops below the pwm to pfm threshold. thereafter the converter continues operation in pfm mode. 7.9 shutdown mode connecting enable to gnd places the tle6389gv in shutdown mode. in shutdown, the reference, control circuitry, external switching mosfet, and the oscillator are turned off and the output falls to 0v. connect enable to voltages higher than 4.5v for normal operation. 7.10 buck converter circuit a typical choice of external components for the buck converter circuit is given in figure 2 and 3. for basic operation of the buck converter the input capacitors c in1 , c in2 , the driver supply capacitor c bds , the sense resistor r sense , the pmos device, the catch diode d1, the induuctance l1 and the output capacitor c out are necessary. in addition for low electromagnetic emission a pi-filter at the input and/or a small resistor in the path between gdrv and the gate of the pmos may be necessary. 7.10.1 buck inductance (l1) selection in terms of ripple current: the internal pwm/pfm control loop includes a slope compensation for stable operation in pwm mode. this slope compensation is optimzed for inductance values of 47h and v drop i load r ds on () pmos r sense r inductance ++ () ? =
tle 6389 preliminary data sheet rev. 1.0 31 2003-05-05 sense resistor values of 50m ? for the 5v output voltage versions. when choosing an inductance different from 47h the sense resistor has to be changed also. to achieve the same effect of slope compensation in the adjustable voltage version also the inductance in h is given by the inductance value determines together with the input voltage, the output voltage and the switching frequency the current ripple which occurs during normal operation of the step down converter. this current ripple is important for the all over ripple at the output of the switching converter. . when picking finally the inductance of a certain supplier (epcos, coilcraft etc.) the saturation current has to be considered. the saturation current value of the desired inductance has to be higher than the maximum load current which can appear in the actual application. 7.10.2 determining the current limit the peak current which the buck converter is able to provide is determined by the peak current limit threshold voltage v lim and the sense resistor r sense . with a maximum peak r sense l1 ------------------- 1064 , 3 10 = 94 v vout r sense ?? () l1 188 v vout r sense ?? () << ? i v in v out ? () v out ? f sw v in l1 ?? ------------------------------------------------------ =
tle 6389 preliminary data sheet rev. 1.0 32 2003-05-05 current given by the application ( i peak, pwm =i load +0.5 ? i) the sense resistor is calculated to 7.10.3 pfm and pwm thresholds the crossovering thresholds pfm to pwm and vice versa strongly depend on the input voltage v in , the buck converter inductance l1, the sense resistor value r sense and the turn on and turn off delays of the external pmos. for more details on the pfm to pwm and pwm to pfm thresholds please refer to the application note ?tle6389 - determining pfm/pwm current thresholds?. 7.10.4 buck output capacitor (c out ) selection: the choice of the output capacitor effects straight to the minimum achievable ripple which is seen at the output of the buck converter. in continuous conduction mode the ripple of the output voltage equals: from the formula it is recognized that the esr has a big influence in the total ripple at the output, so low esr tanatlum capacitors are recommended for the application. one other important thing to note are the requirements for the resonant frequency of the output lc-combination. the choice of the components l and c have to meet also the specified range given in section 3 otherwise instabilities of the regulation loop might occur. 7.10.5 input capacitor (c in1 ) selection: at high load currents, where the current through the inductance flows continuously, the input capacitor is exposed to a square wave current with its duty cycle v out /v i . to r sense v lim 2i ? peak pwm , ------------------------------------ - = v ripple ? ir esrcout 1 8f sw c out ?? ----------------------------------- - + ? =
tle 6389 preliminary data sheet rev. 1.0 33 2003-05-05 prevent a high ripple to the battery line a capacitor with low esr should be used. the maximum rms current which the capacitor has to withstand is calculated to: for low esr an e.g. al-electrolythic capacitance in parallel to an ceramic capacitance could be used. 7.10.6 freewheeling diode / catch diode (d1) for lowest power loss in the freewheeling path schottky diodes are recommended. with those types the reverse recovery charge is neglectible and a fast handover from freewheeling to forward conduction mode is possible. depending on the application (12v battery systems) 40v types could be also used instead of the 60v diodes. also for high temperature operation select a schottky-diode with low reverse leakage. a fast recovery diode with recovery times in the range of 30ns can be also used if smaller junction capacitance values (smaller spikes) are desired. 7.10.7 buck driver supply capacitor (c bds ) the voltage at the ceramic capacitor is clamped internally to 7v, a ceramic type with a minimum of 220nf and voltage class 16v would be sufficient. 7.10.8 input pi-filter components for reduced eme at the input of buck converters a square wave current is observed causing electromagnetical interference on the battery line. the emission to the battery line consists on one hand of components of the switching frequency (fundamental wave) and its harmonics and on the other hand of the high frequency components derived from the current slope. for proper attenuation of those interferers a -type input filter structure is recommended which is built up with inductive and capacitive components in addition to the input caps c in1 and c in2 . the inductance can be chosen up to the value of the buck converter inductance, higher values might not be necessary, the additional capacitance should be a ceramic type in the range up to 100nf. inexpensive input filters show due to their parasitrics a notch filter characteristic, which means basically that the lowpass filter acts from a certain frequency as a highpass filter and means further that the high frequency components are not attenuated properly. to slower down the slopes at the gate of the pmos switch and get down the emission in the high frequency range a small gate resistor can be put between gdrv and the pmos gate. i rms i load v out v in -------------- 1 1 3 -- - ? i 2i load ? ----------------------- 2 ? + ?? =
tle 6389 preliminary data sheet rev. 1.0 34 2003-05-05 7.11 components recommendation - overview 7.12 layout recommendation the most sensitive points for buck converters - when considering the layout - are the nodes at the input, output and the gate of the pmos transistor and the feedback path. for proper operation and to avoid stray inductance paths the external catch diode, the buck inductance and the input capacitor c in1 have to be connected as close as possible to the pmos device. also the gdrv path from the controller to the mosfet has to be as short as possible. best suitable for the connection of the cathode of the catch diode and one terminal of the inductance would be a small plain located next to the drain of the pmos. the gnd connection of the catch diode must be also as short as possible. in general the gnd level should be implemented as surface area over the whole pcb as second layer, if necessary as third layer. the feedback path has to be well grounded also, a ceramic capacitance might help in addition to the output cap to avoid spikes. device type supplier remark c in1 electrolythic /foil type various 100 f, 60v c in2 ceramic various 220nf, 60v l1 b82464-a4473 epcos 47 h, 1.6a, 145m ? b82479-a1473-m epcos 47 h, 3.5a, 47m ? do3340p-473 coilcraft 47 h, 3.8a, 110m ? do5022p-683 coilcraft 68 h, 3.5a, 130m ? ds5022p-473 coilcraft 47 h, 4.0a, 97m ? m1 bso 613spv infineon 60v, 3.44a, 130m ? , nl bsp 613p infineon 60v, 2.9a, 130m ? , nl spd09p06pl infineon 60v, 9a, 250m ? , ll c bds ceramic various 220nf, 16v d1 mbrd360 motorola schottky, 60v, 3a mbrd340 motorola schottky, 40v, 3a ss34 various schottky, 40v, 3a c out b45197-a2107 epcos low esr tantalum, 100 f, 10v
tle 6389 preliminary data sheet rev. 1.0 35 2003-05-05 to obtain the optimum filter capability of the input pi-filter it has to be located also as close as possible to the input. to filter the supply input of the device (vs) the ceramic cap should be connected directly to the pin. as a guideline an emc optimized application board / layout is available.
tle 6389 preliminary data sheet rev. 1.0 36 2003-05-05 8 package outlines: dimensions in mm
tle 6389 preliminary data sheet rev. 1.0 37 2003-05-05 published by infineon technologies ag, st.-martin-strasse 53, d-81541 mnchen, germany ? infineon technologies ag 2003 all rights reserved. attention please! the information herein is given to describe certain components and shall not be considered as warranted characteristics. terms of delivery and rights to technical change reserved. we hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. infineon technologies is an approved cecc manufacturer. information for further information on technology, delivery terms and conditions and prices please contact your nearest infineon technologies office in germany or our infineon technologies representatives worldwide. warnings due to technical requirements components may contain dangerous substances. for information on the types in question please contact your nearest infineon technologies office. infineon technologies components may only be used in life-support devices or systems with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered.

▲Up To Search▲

Price & Availability of TLE6389-G50

	To Download TLE6389-G50 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .